A related patent application is a commonly assigned Japanese Patent Application No. 2001-301180 filed on Sep. 28, 2001, which is incorporated by reference into the present patent application.
1. Field of the Invention
The present invention relates to a method of producing a semiconductor device having multi-layer wiring structure and the structure of such a semiconductor device, and more particularly, to a method adopting damascene process for producing a semiconductor device having a multi-layer wiring and the structure of such a semiconductor device.
2. Description of the Related Art
FIG. 10 shows a semiconductor device having conventional multi-layer wiring structure indicated in its entirety by 600. In the semiconductor device 600, there is an insulation layer 102 of silicon oxide disposed on a silicon substrate 101. Formed on the insulation layer 102 is an SOI (Silicon On Insulator) transistor (thin film transistor) indicated in its entirety by 110. The SOI transistor 110 includes a channel layer 113 located between a source 111 and a drain 112, a gate electrode 114 disposed on the channel layer 113, and a side wall 115. An inter-layer insulation layer 103 and a multi-layer wiring 120 are formed on the SOI transistor 110. The multi-layer wiring 120 consists of contact plugs 121 connected to the source 111 or the drain 112 of the SOI transistor 110 and a wiring layer 122 which connects the contact plugs 121 to each other.
When the inter-layer insulation layer 103 is deposited on the SOI transistor 110, asperities owing to the gate electrode and the like cause differences in level to be created on the surface of the inter-layer insulation layer 103 as shown in FIG. 11. This makes it difficult to create a focus margin for a lithography step of forming the contact plugs 121 and the like in the inter-layer insulation layer 103, and especially, to form the contact plugs 121 and the like when the contact plugs 121 and the like are to be formed in minute patterns. While an alternative approach is planarization of the surface of the inter-layer insulation layer 103 by the CMP method, since such planarization has a limitation, it is difficult to ensure that the surface is sufficiently flat to form the contact plugs and the like as minute patterns.
In addition, there is a limit to improvement in density of wiring even by means of a multi-layer wiring structure as that shown in FIG. 10.
The present invention aims at providing a method of producing a semiconductor device having a multi-layer wiring structure of minute definition and high density as well as the structure of such a semiconductor device.
The present invention is directed to a producing method of producing a semiconductor device including an SOI transistor and a multi-layer wiring. The method includes a step of preparing a silicon substrate having a front face and a back face; an inter-layer insulation layer forming step of forming an inter-layer insulation layer on the front face of the silicon substrate; a wiring step of forming a multi-layer wiring in the inter-layer insulation layer; a substrate fixing step of fixing a substrate on the inter-layer insulation layer; an SOI layer forming step of thinning the silicon substrate from the back face into a thin film so that the silicon substrate becomes an SOI layer; and a transistor forming step of forming a channel layer and a gate electrode on a back face of the formed channel layer, in the SOI layer and further forming a source and a drain facing each other having the channel layer in between so that an SOI transistor is obtained.
The present invention is also directed to a semiconductor device having an SOI transistor and a multi-layer wiring. The device includes a substrate; an inter-layer insulation layer disposed on the substrate; and on the inter-layer insulation layer disposed an SOI transistor including a gate electrode on the opposite side to the substrate. A multi-layer wiring connected with the SOI transistor is provided within the inter-layer insulation layer.